A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI:10.1109/CICC53496.2022.9772865

Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun

{"title":"A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM","authors":"Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun","doi":"10.1109/CICC53496.2022.9772865","DOIUrl":null,"url":null,"abstract":"CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC53496.2022.9772865","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

Abstract

CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.

查看原文本刊更多论文

基于低成本二阶矢量量化DEM的0.37mm2 250kHz-BW 95dB-SNDR CTDSM

工业、医疗和汽车应用需要高分辨率和带宽大于200kHz的ctdsm。如此高的性能要求非常低的噪音和失真。由于低电压净空，在先进技术中必须进一步抑制噪声和失真。低噪声和低失真设计的一个主要挑战是DAC和环路滤波器的大面积成本。主反馈RDAC在[1]中占有较大的面积。该方法采用一阶数据加权平均(DWA)，但对失配误差的抑制有限。在低输入幅度下，由于DWA引起的音调，在SNDR图[1]中也存在一个扭结。为了减小面积，[2]，[3]对MSB位使用DWA，对LSB位使用不匹配误差整形(MES)。MES允许二进制编码的DAC保存LSB DAC区域。然而，整个DAC的不匹配引起的失真是由MSB位主导的。因此，[2]，[3]的方法由于在MSB位上的DWA操作获得的相对温和的一阶失配误差整形而产生有限的性能优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2022 IEEE Custom Integrated Circuits Conference (CICC)

自引率

0.00%

发文量