Parasitic-aware synthesis of RF CMOS switching power amplifiers

Abstract

Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.