A 3D hybrid integration methodology for terabit transceivers

Abstract

This paper presents a three-dimensional (3D) hybrid integration methodology for terabit transceivers. The simulation methodology for multi-conductor structures are explained. The effect of ground vias on the RF circuitry and the preferred interposer substrate material for large bandwidth 3D hybrid integration are described. An equivalent circuit model of the via-throughs connecting the RF circuitry to the modulator is proposed and its lumped element parameters are extracted. Wire bonding transitions between the driving and RF circuitry were designed and simulated. An optimized 3D interposer design demonstrated a simulated -3 dB transmission bandwidth up to 95 GHz with associated return loss better than 10 dB. A thermal analysis of a subassembly for the packaged transmitter module is performed. A maximum temperature of 74 °C is predicted when copper-tungsten is used as the material of the sub-mount and heat sink layer.