An Efficient Genetic Algorithm Based Multi-objective Optimization Technique for VLSI Circuit Partitioning with Reduced Power Consumption

Abstract

Very large scale integration (VLSI) design and automation is one of the most important fields from decades. But still now VLSI physical design has high demand. Efficient methods are still in demand to reduced area of the circuit, cost of implementation, delay of circuit operation and power consumption of the circuit. In this paper an evolutionary genetic algorithm based multi-objective optimization strategy has been presented that minimizes net cut and delay time but maximizes sleep duration in VLSI circuit partitioning. As a result, the partitioning solution consumes least amount of power. Use of k-way partition has balanced the circuit as much as possible. All the circuit module including input-output (IO) pads are converted into a hyper graph. At each generation fitness value has been evaluated and all the solutions which have low fitness value have been discarded. The proposed method has been evaluated on the net list files of ISPD’98 circuit benchmark suite where each circuit contains 90 to 100 nodes and 100 to 175 nets. In this experiment 8-way partitioning has been implemented. Experimental results shows that the average net cut size, delay and sleep time are 78, 63, and 3.73 micro seconds respectively. The quality of solutions generated by proposed evolutionary algorithm is supported by domain experts. It is found that the system’s overall average power saving for 8-way partitioning is 3038 mW.