Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems

Abstract

This paper describes a proposal for FAT tree based Network-on-Chip system based on MPLS forwarding mechanism. The FAT tree includes processing nodes and communication switches. IP node (processing nodes) has a message generator unit which randomly generates messages to different destinations with different packet lengths and buffering. The switch is based on MPLS technique and consists of the following units: crossbar switch, input/output link controllers and routing and arbitration units. A simulator has been developed in C++ to analyze the proposed architecture. A comparison with wormhole switch is provided to show the efficiency of the MPLS designed switch.