High-level data path synthesis for built-in self-test designs

Abstract

The sharing of modules and test registers ensures only a small number of registers is modified for BIST, thereby decreasing the hardware area which is one of the major overhead for BIST technique. In this approach, both module allocation and register allocation are performed incrementally. In each iteration, module allocation is guided by a testability balance technique while register allocation aims at increasing the sharing degrees of registers. In this paper, we would like present two improvement techniques, namely the resource optimization approach before the synthesis algorithm and high-level automatic BIST configuration after the synthesis algorithm. With a variety of benchmarks, we demonstrate the advantage of the improvement approaches compared with previous results.