A CNN motivated array computing model

Abstract

Approaching the limits of scaling down of CMOS circuits where transistors can switch faster and faster transmitting information between different areas of an integrated circuit has great importance. The speed of signals are determined by the physical properties of the medium therefore the distance between the elements should be decreased to improve performance. Array processors are a good candidate to solve this problem. Similar approach is required on today high performance field programmable logic devices where wire delay dominates over gate (LUT) delay. Centralized control unit of a configurable accelerator might become a performance bottleneck on the current state-of-the-art FPGAs. In the paper a process network inspired approach is given to create distributed control units. The advantage of the proposed method will be shown by designing a complex multi-layer array computing architecture to emulate the operation of a mammalian retina in real time.