Evolutionary Synthesis of Synchronous Finite State Machines

Abstract

Synchronous finite state machines are very important for digital sequential designs. They allow the synchronisation of the hardware system components so that these may cooperate adequately in the fulfillment of the main objective of the design. In this paper, assuming that the state assignment problem has been solved and so a specific state coding is provided, we propose to me the evolutionary methodology to yield optimal evolvable hardware that implements the state machine control component. The evolved hardware requires a minimal hardware area and introduces a minimal propagation delay of the machine output signals