{"title":"Design of content addressable memory cell using carbon nanotube field effect transistors","authors":"Subhajit Das, Debaprasad Das, H. Rahaman","doi":"10.1109/TECHSYM.2016.7872669","DOIUrl":null,"url":null,"abstract":"This paper presents design and analysis of low voltage stable SRAM based 11-transistor high speed content addressable memory (CAM) unit using dual gate (DG) Schottky-barrier carbon nanotube field effect transistor (SB-CNTFET). The 8-transistor highly stable SRAM counterpart of CAM cell contains six p-type and two n-type dual gate SB-CNTFETs where the searching network adds three more p-type transistors. The circuit compatible model of dual gate SB-CNTFET operates steadily at 0.5 V power supply. The design is implemented with Si-MOSFET, MOSFET-like CNTFET and DG SB-CNTFET. For the proposed low voltage SRAM based DG SB-CNTFET CAM cell, we have achieved 120× lesser power-delay-product (PDP) during read operation, 845× lesser PDP during write operation and 407× lesser PDP during search operation compared to similar design using Si-MOSFET. The DG SB-CNTFET based CAM also shows ∼2× less PDP during read-write-search operations as compared to the MOSFET-like CNTFET based CAM cell.","PeriodicalId":403350,"journal":{"name":"2016 IEEE Students’ Technology Symposium (TechSym)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Students’ Technology Symposium (TechSym)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TECHSYM.2016.7872669","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents design and analysis of low voltage stable SRAM based 11-transistor high speed content addressable memory (CAM) unit using dual gate (DG) Schottky-barrier carbon nanotube field effect transistor (SB-CNTFET). The 8-transistor highly stable SRAM counterpart of CAM cell contains six p-type and two n-type dual gate SB-CNTFETs where the searching network adds three more p-type transistors. The circuit compatible model of dual gate SB-CNTFET operates steadily at 0.5 V power supply. The design is implemented with Si-MOSFET, MOSFET-like CNTFET and DG SB-CNTFET. For the proposed low voltage SRAM based DG SB-CNTFET CAM cell, we have achieved 120× lesser power-delay-product (PDP) during read operation, 845× lesser PDP during write operation and 407× lesser PDP during search operation compared to similar design using Si-MOSFET. The DG SB-CNTFET based CAM also shows ∼2× less PDP during read-write-search operations as compared to the MOSFET-like CNTFET based CAM cell.