Performance Enhancement of SoC with Five Port Router by Replacing APB Protocol

Abstract

A In today's technological development and the advancement in IC technology, a huge number of intellectual property (IP)cores can be consolidated onto a single chip. Due to this, communication between the IP cores becomes more difficult. To overcome the restriction of this communication, we introduce a technology called NETWORK ON CHIP(NoC). This is an on-chip packet-switched network with IP cores connected to the network via interfaces, and the packets are sent to their respective destination to a multi-chip routing path. A router is an essential component for NoC architecture. The design had to be done effectively to build a competitive NoC architecture. In this proposed work router can be designed using Verilog. It has stored a forward type of flow control round robin arbitration and deterministic XY routing. The essential parts for a router are FIFO, arbiter, and crossbar. The plan behind the five-port router is intended to be used with the FPGA design platform to test the functionality of the NoC on hardware. The outline of the router is designed through Verilog and simulated using zynq board 7000 series and verified using system Verilog, and its feasible model is also verified.