Lifting of the 9/7 Wavelet Filter Bank for ECG Signal Analysis Implementation Based on FPGA Target

Farouk Boumehrez, A. Sahour, Fouzia Maamri, Hanane Djellab
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Abstract

The electrocardiogram (ECG) signal is often used in healthcare as one of the most significant methods for determining the cardiac condition of a patient. It represents the variations of the electrical activity of the heart as a function of time. This paper presents the hardware Implementation OF THE Lifting 9/7 Wavelet Filter Bank ECG Signal Analysis on cyclone-II EP2C35F72C6 FPGA in Altera DE2 board using VHDL Hardware Description Language (HDL). Quartus-II version 8.1 is a synthesis software tool and ModelSim Altera WEB edition 6.4a is used as a simulator Multiply/divide operations using left/right shifters are used in contrast to standard operations with the aim of reducing time execution, the number of elementary logic, and power consumption.
基于FPGA的9/7小波滤波器组心电信号分析实现
心电图(ECG)信号在医疗保健中经常被用作确定患者心脏状况的最重要方法之一。它代表了心脏电活动随时间的变化。本文介绍了在Altera DE2板上使用VHDL硬件描述语言在cyclone-II EP2C35F72C6 FPGA上实现升降9/7小波滤波器组心电信号分析的硬件实现。Quartus-II版本8.1是一个合成软件工具,ModelSim Altera WEB版本6.4a被用作模拟器。与标准操作相比,使用左/右移位器进行乘/除操作,目的是减少执行时间、基本逻辑的数量和功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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