{"title":"Voltage controlled dielectric resonator oscillator using microstrip fed slot excited cylindrical DR","authors":"S. Srikanth, M. Adhikary, A. Biswas, M. Akhtar","doi":"10.1109/AEMC.2017.8325700","DOIUrl":null,"url":null,"abstract":"In this paper, a novel voltage tuned dielectric resonator oscillator (Vt-DRO) is designed. A microstrip fed slot excited cylindrical DR is used as a terminating network. The frequency tuning is achieved by placing a varactor in shunt with the DR and varying its reverse bias voltage. An MA 46 series varactor is used for tuning purpose and the reverse bias is applied separately other than the transistor bias. The Vt-DRO is implemented using the negative resistance approach and is composed of three blocks: dielectric resonator, active network and the load network. The measured phase noise of the Vt-DRO is −90 dBc/Hz at an offset of 2 MHz. A very broad tuning range of around 225 MHz is achieved for tuning voltage of 0 to 16 V and the measured power level is around 0dBm.","PeriodicalId":397541,"journal":{"name":"2017 IEEE Applied Electromagnetics Conference (AEMC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Applied Electromagnetics Conference (AEMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AEMC.2017.8325700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, a novel voltage tuned dielectric resonator oscillator (Vt-DRO) is designed. A microstrip fed slot excited cylindrical DR is used as a terminating network. The frequency tuning is achieved by placing a varactor in shunt with the DR and varying its reverse bias voltage. An MA 46 series varactor is used for tuning purpose and the reverse bias is applied separately other than the transistor bias. The Vt-DRO is implemented using the negative resistance approach and is composed of three blocks: dielectric resonator, active network and the load network. The measured phase noise of the Vt-DRO is −90 dBc/Hz at an offset of 2 MHz. A very broad tuning range of around 225 MHz is achieved for tuning voltage of 0 to 16 V and the measured power level is around 0dBm.