Automatic incorporation of on-chip testability circuits

Abstract

A system which automatically incorporates testability circuits into ECL chips is presented. Three types of circuits are incorporated: (1) a random access scan circuit, (2) a clock suppression circuit for delay fault testing, and (3) a pin scan-out circuit for chip I/O pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. This system was used to develop the new Fujitsu VP-2000 supercomputer.<>