A low power variable sized CSLA implementation using GDI logic in 45nm SOI technology

Abstract

Adders are an integral part of the modern day processor; Carry select adders (CSLA) being one of the commonly used efficient adders. But this efficiency comes with the cost of a larger area and higher power dissipation. Over time, down-scaling the transistor sizes have reduced the area; but due to the CMOS logic style designing, the circuit still remains complex. Hence, in this paper a gate-level modification method called Gate Diffusion Input (GDI) is used to implement the CSLA in order to reduce the power, delay and area. The standard CMOS CSLA is compared with GDI logic CSLA designed in 45nm Technology node. The analysis shows that GDI based logic style is simple in terms of transistor count and provides better performance compared to the standard CMOS logic style.