Energy Efficient Loop Unrolling for Low-Cost FPGAs

Abstract

Many FPGA computations, including block ciphers, require repetitive loop operations that are difficult to parallelize. Sequential loop implementation leads to significant clock powerwhile loop unrolling can lead to significant glitch power. In thispaper, we provide a low overhead approach to unroll blockciphers and other loops in low-cost FPGAs to reduce energyconsumption. A latch-based glitch filter is introduced for unrolledloops that reduces loop energy per operation by over an order ofmagnitude. Our filters and associated control for unrolled loopscan be automatically instantiated as a macro for FPGA designs, allowing for easy designer use. We demonstrate our approach forSIMON-128 and AES-256 block ciphers implemented on a XilinxArtix-7 FPGA.