Extraction of Aspect Ratio for Non-Manhattan CMOS Devices

Abstract

Non-Manhattan CMOS devices are gaining attention because of their special properties. In this paper waffle and closed gate structures are discussed and issues related to their use in CAD tools are addressed. The waffle devices are used where large aspect ratio with low parasitic capacitances and lower silicon overhead is required. The closed-gate layout is used in rad-hard digital libraries due to their edgeless geometry. These devices are difficult to handle because Process Design Kit (PDK) is developed for Manhattan geometries. This paper discusses how the models for Manhattan devices can’t be extended to predict accurate I-V characteristics of the non-manhattan devices. An analytical model is developed to map non-Manhattan devices to equivalent Manhattan devices. A test chip in 0.7?m CMOS technology was developed to validate the concept. The PDK was modified to introduce these structures in normal analog design flow.