Design and Simulation of Parallel BCH Code with LDPC Code For Flash Memories

Abstract

Ensuring data reliability and adapting a very powerful error correction code of flash memory and DVB-S2 became a strategic demand nowadays. LDPC codes are designed for their high error correcting ability. Meanwhile, the error floor of LDPC codes cannot satisfy the significant low error rate requirements of flash memory applications. Therefore, we take into account a concatenated BCH and LDPC coding system for the potential usage of data preventive on flash memory. To solve this problem, the concatenation of BCH and LDPC code is performed. The result is a better balance between the potential to correct errors and the low error rate, which can be an optional coding structure. In this paper, our objective is to design a parallel BCH code concatenated with LDPC code to enhance BER and minimize the low error floor. Additionally, our purpose is to figure out the least number of BCH branches that achieve the best BER and consume the least hardware resources.