Identification of DRAM sense amplifier imbalance using hot carrier evaluation

Abstract

The authors present a study of the causes of inherent imbalance in a DRAM sense amplifier. Refresh time measurements are used to assess this imbalance before and after hot carrier stress. The stress effect on the sense amplitude is compared to simulations using a circuit hot electron effect simulator. This analysis shows that the latch transistor threshold voltage variation, rather than layout capacitance difference, is the cause for the original imbalance.<>