Analysis and Implementation of a Low Power Sense Amplifier based flip flop with symmetric latch design

Abstract

In this paper, sense amplifier based flip flop (SAFF) with different latch designs is implemented and analyzed with respect to minimum voltage supply, delay and power. The conventional SAFF along with Power PC Master Slave flip flop (MSFF) and Pulse triggered flip flop (PTFF) are also discussed. In the result section, the output waveform and parametric analysis of all the SAFFs are implemented and results of comparison of each schematic are also discussed. The schematic of all the flip flops are designed using gdpk90nm and simulated using cadence tool.