Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip

Abstract

With increasing number of processing elements on a single chip, the size of the Network-on-Chip connecting the processing elements increases accordingly. This leads to new challenges for components such as fault diagnosis and routing because they do not scale with the size of the Network-on-Chip, e.g. regarding the required communication overhead or their implementation costs. A measure to avoid these scaling problems is to organize future Networks-on-Chip hierarchically. This paper presents a fault tolerant routing for Networks-on-Chip organized into hierarchical units where each unit manages its own routing. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16x16 network show a speedup of three for routing reconfiguration compared to state-of-the-art approach. At the same time our approach achieves a memory reduction for routing tables by a factor of seven compared to flat network tables.