A Novel Super-Steep Slope (~0.015mV/dec) Gate-Controlled Thyristor (GCT) Functional Memory Device to Support the Integrate-and-Fire Circuit for Spiking Neural Networks
Cheng-Lin Sung, H. Lue, M. Wei, S. Ho, Han-Wen Hu, P. Du, Wei-Chen Chen, C. Lo, T. Yeh, Keh-Chung Wang, Chih-Yuan Lu
{"title":"A Novel Super-Steep Slope (~0.015mV/dec) Gate-Controlled Thyristor (GCT) Functional Memory Device to Support the Integrate-and-Fire Circuit for Spiking Neural Networks","authors":"Cheng-Lin Sung, H. Lue, M. Wei, S. Ho, Han-Wen Hu, P. Du, Wei-Chen Chen, C. Lo, T. Yeh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IEDM13553.2020.9372094","DOIUrl":null,"url":null,"abstract":"The analog neuromorphic circuits with functional memory devices are considered as an ultimate ideal approach to mimic the human brain for artificial intelligence (AI). The spiking neural network (SNN) with integrate-and-fire (IF) circuit is the classic building block theoretically, but so far it is very difficult to find ideal devices to realize the SNN circuit. In this work, we propose a novel functional memory that is enabled by a novel thyristor, which features super-steep slope (S.S.~0.015mV/dec), large ON/OFF ratio (> 5 orders), and tunable Vth range (0~3V). These are very ideal to meet the IF circuit requirements. Circuit and network simulations indicate that the gate-controlled thyristor (GCT) device for the IF circuit can realize high accuracy and performance for image recognition SNN. Our novel SNN architecture with the GCT device can provide good energy efficiency (equivalent to 181TOPS/W for accumulation operations), good error tolerance to Vth variations (~10% range), and substantially smaller circuit area than that using conventional CMOS devices for IF circuit.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"422 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9372094","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The analog neuromorphic circuits with functional memory devices are considered as an ultimate ideal approach to mimic the human brain for artificial intelligence (AI). The spiking neural network (SNN) with integrate-and-fire (IF) circuit is the classic building block theoretically, but so far it is very difficult to find ideal devices to realize the SNN circuit. In this work, we propose a novel functional memory that is enabled by a novel thyristor, which features super-steep slope (S.S.~0.015mV/dec), large ON/OFF ratio (> 5 orders), and tunable Vth range (0~3V). These are very ideal to meet the IF circuit requirements. Circuit and network simulations indicate that the gate-controlled thyristor (GCT) device for the IF circuit can realize high accuracy and performance for image recognition SNN. Our novel SNN architecture with the GCT device can provide good energy efficiency (equivalent to 181TOPS/W for accumulation operations), good error tolerance to Vth variations (~10% range), and substantially smaller circuit area than that using conventional CMOS devices for IF circuit.