A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology

Abstract

A reduced interface and high performance embedded system architecture (MSBUS) is proposed in this paper. The control bus is low-cost and low-power, whereas the data bus is high-bandwidth and high-speed especially. In addition, a Universal Verification Methodology (UVM)-based performance evaluation methodology is proposed to estimate the hardware structures. In order to evaluate the bus performance, AHB, AXI and MSBUS DMA are implemented as a case study. The experimental results show that MSBUS DMA uses the least hardware resources, reduces energy consumption to a half of AHB and AXI in the block transfer mode, and achieves 3.3 times and 1.6 times valid bandwidth of AHB and AXI respectively. Moreover, the proposed evaluation methodology is effectively used with sufficient accuracy.