Structural Design of an Electrically Erasable EEPROM Memory Cell

Abstract

EEPROM is an electrically erasable and programmable memory. The technology is mature and stable with low cost, so it is the mainstream in the application of electronic products in daily life. People use it in every way. In the fields of personal identity card, bank card, medical insurance card, traffic card and other smart cards, which are closely related to personal property, and in the field of communication system and other consumer electronic products such as PDA and digital camera, EEPROM is used. In instruments and other embedded systems, such as smart flowmeters, it is usually necessary to store information such as setting parameters, field data, etc., which requires that the system is not lost when it is powered down so that the data you originally set could be restored next time. Therefore, a certain capacity of EEPROM. Through the storage or release of electrons on the floating gate tube of the memory cell, the memory appears to be on or off when the floating gate tube is read, so its logic value will be judged as “0” Or “1”. The definition of logic “0” or “1” varies depending on the logical design of the product. This work designs a memory cell consisting of two transistors. The NMOS tube is used as a selection tube and controlled by the word line. It can withstand a part of the high voltage and reduce the probability of breakdown of the ultra-thin oxide layer of the floating gate transistor. As a storage tube, the EEPROM device model designed in this paper can work well through the tunnel oxide layer to store data, achieving better storage functions, higher work efficiency, and lower power consumption.