A 18-24 GHz Compact Single Stage Amplifier with 13 ± 0.5 dB gain, OP3dB of +19 dBm and 19% PAE for Radar Applications in Tower 180 nm CMOS

S. Jameson, N. Buadana, E. Sźulc, A. Sayag, Isaac Sarusi, A. Wolfman, O. Shaham
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Abstract

This paper proposes a modified differential cascode amplifier topology for mm-wave applications requiring wideband amplification, flatness and compact integration area. The proposed topology was used to create a single stage power amplifier with +13 dB small-signal gain ±0.5 dB flatness over 18 - 24 GHz. The power amplifier load-pull and biasing were optimized to reach a maximum PAE around 3 dB compression to minimize AM-PM variation and maximize performance-to-reliability ratio in large phased array transmitters. At 3 dB compression, an output power of +19 dBm with a peak PAE of 19% was measured around 18 GHz. Respectively, at 8 dB compression a peak power of +20 dBm is achieved and is over +19 dBm up to 24 GHz. The circuit demonstrates one of the smallest core area (0.16 mm2) and excellent power density. The proposed topology presents currently a record small signal gain per stage at this technology node ($f_{T}/f_{max}$ of 59/65 GHz). The presented amplifier topology can be used repetitively and reliably to create wide-band amplifiers with state-of-the-art gain, flatness and return loss over small area. The circuit was realized using Tower’s 180 nm CMOS.
18-24 GHz紧凑型单级放大器,增益为13±0.5 dB, OP3dB为+19 dBm, PAE为19%,适用于雷达在180nm CMOS上的应用
本文提出了一种改进的差分级联放大器拓扑结构,用于需要宽带放大、平坦度和紧凑集成面积的毫米波应用。所提出的拓扑结构用于创建一个单级功率放大器,在18 - 24 GHz范围内具有+13 dB小信号增益±0.5 dB平坦度。在大型相控阵发射机中,对功率放大器的负载-拉和偏置进行了优化,以达到约3db压缩的最大PAE,从而最小化AM-PM变化并最大化性能-可靠性比。在3db压缩时,在18ghz附近测量到的输出功率为+ 19dbm,峰值PAE为19%。在8 dB压缩时,峰值功率分别达到+20 dBm,在24 GHz时峰值功率超过+19 dBm。该电路具有最小的核心面积(0.16 mm2)和优异的功率密度。所提出的拓扑目前在该技术节点(59/65 GHz的$f_{T}/ $f_{max}$)上每级的信号增益创历史记录。所提出的放大器拓扑结构可以重复可靠地用于创建具有最先进的增益、平坦度和小面积回波损耗的宽带放大器。该电路采用Tower的180nm CMOS实现。
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