Timing closure of clock enable signals on a 32 nm Intel Itanium processor

Abstract

With modern high speed circuit design using state of the art automated place and route (APR) flows, synthesis of clock enable (CE) signals is becoming increasingly difficult in terms of timing closure. The size of APR blocks in digital physical design in microprocessor projects is expanding with every generation of microprocessors as the implementation tools become more capable of handling large designs with high quality results and fast turnaround times. However, larger APR blocks make CE synthesis progressively difficult as timing closure complexity on these signals increases dramatically. The main problem is due to a single CE register driving the signal to a relatively larger area of the design, and to a greater number of clock gating cells. In this paper, we present automated duplication of CE logic in the APR flow to achieve timing closure on a 32 nm Intel Itanium project. We show how timing convergence is achieved without any additional effort from the physical designers, and with no changes required in the RTL. Solutions to the CE problem with smaller degree of automation and more manual effort, which were used on our previous projects, are also discussed and compared, and the reasons they are deemed inadequate are explained.