Dataflow to Hardware Synthesis Framework on FPGAs

Abstract

We present a dataflow based performance estimation and synthesis framework that will help hardware designers quantify the algorithm performance and synthesize their HW designs onto Field Programmable Gate Arrays (FPGAs). Typically, Digital Signal Processing (DSP) systems are designed by making gradual architectural choices in HW refinement steps. These decisions are based on performance quantification by high level DSP algorithm developers and HW implementation engineers. The main obstacle to this refinement is the provision of reasonably correct performance estimations to guide HW designers in Design Space Exploration (DSE) at an early stage. HW designers face challenges when they need to quantify the performance of their designs, especially when resources are limited. We use dataflow models by describing their hardware detail only as necessary. Dataflow based performance estimation achieves the efficient generation of qualitative and quantitative parameters for the assessment of HW candidates. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, FPGAs can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration from the dataflow to synthesized HDL design. Experimental results show a linear speedup by adding reasonably small processing elements in FPGA as opposed to using a software implementation running on a typical general purpose processor.