Improving the efficiency of power simulators by input vector compaction

Abstract

Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input vector set must be used which leads to very long simulation time. One solution is to generate a compact vector set that is representative of the original input vector set and can be simulated in a reasonable time. We propose an input vector compaction technique that preserves the statistical properties of the original sequence. Experimental results show that a compaction ratio of 100X is achieved with less than 2% average error in the power estimates.