Three-dimensional very thin stacked packaging technology for SiP

Abstract

In order to achieve the greater compactness, lightness, high- and multi-functionality required of mobile equipment and other electronic devices, we have developed 3D packaging technology which enables free stacking, at the package level, of ultra-thin CSP (which contain 2 or 1 LSI chip(s)). By stacking at the package level, there are no yield problems, and it is easy to perform independent electrical testing, so it is possible to achieve multi-level stacking while freely combining different kinds of LSI chips like memory or ASIC. By making chips and resin molding thinner, lowering wire loops and optimizing the package structure, we achieved higher package density: a single unit (2 chips) package height of 0.55 mmMax., 2 layers (4 chips) with a unit package height of 1.0 mmMax., and 3 layers (6 chips) with a unit package height of 1.5 mmMax. This technology makes it possible to offer ultra-compact systems-in-package (logic + memory) and high-capacity composite memories.