Cache Memory: An Analysis on Performance Issues

Sonia, Ahmad Alsharef, Pankaj Jain, Monika Arora, Syed Rameem Zahra, Gaurav Gupta
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引用次数: 13

Abstract

Cache memory is mainly inculcated in systems to overcome the gap created in-between the main memory and CPUs due to their performance issues. Since, the speed of the processors is ever-increasing, so a need arises for a faster speed cache memory that can definitely assist in bridging the gap between the speed of processor and memory. Therefore, this paper proposes architecture circumscribed with three improvement techniques namely victim cache, sub-blocks, and memory bank. These three techniques will be implemented one after other to improve and make the speed and performance of cache comparative to main memory. Moreover, the different variables like miss penalty ratio, access speed of cache and miss rate ratio, which were already in use, are used in this paper to estimate the cache memory performance after implementation of proposed approach. After performance estimation it can be determined that proposed approach at level 1, using Victim Cache technique decreases the rate of misses, at level 2, Subblocks Division technique further reduces the penalty ratio of miss rate and then at level 3 Memory Bank Technique is useful in further decreasing memory access time. Thus, using the suggested approach, performance of Cache Memory can be improved several times.
高速缓存:性能问题分析
高速缓存主要用于系统中,以克服由于性能问题而在主存和cpu之间产生的差距。由于处理器的速度在不断提高,因此需要更快的高速缓存,以帮助弥合处理器和内存之间的速度差距。因此,本文提出了以受害者缓存、子块和内存库三种改进技术为框架的体系结构。这三种技术将依次实现,以提高高速缓存的速度和性能,使其与主存相媲美。此外,本文还利用已使用的缺失惩罚率、缓存访问速度和缺失率等不同变量来评估实现该方法后的缓存性能。经过性能评估,可以确定所提出的方法在第1级,使用受害者缓存技术降低了失球率,在第2级,子块分割技术进一步降低了失球率的惩罚比率,然后在第3级,内存库技术有助于进一步减少内存访问时间。因此,使用建议的方法,缓存内存的性能可以提高几倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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