Are standalone gate size and VT optimization tools useful?

Abstract

Many algorithms for gate size and threshold voltage (VT) optimization have been proposed. The International Symposium of Physical Design (ISPD) contests for discrete gate sizing with wire loads have led to improved algorithms. However, significant changes in cell sizes require re-placement and re-routing which invalidate the wire loads upon which the sizing was performed. In turn, sizing must be re-performed with new wire loads. To best of our knowledge, it has not been shown how much leakage power reduction can be obtained for actually laid out circuits, nor whether the process even converges. In this work, we chose a gate size and VT optimization algorithm which achieves leakage reduction results comparable to best reported to date for smaller circuits and better results for the largest circuits in the ISPD set. We interfaced the tool with leading EDA tools using a 45nm multi-VT cell library. We propose an incremental placement and routing methodology for use with the EDA placement and routing tool, such that the post-sizing placement and routing converges to the solution achieved after sizing and VT optimization. The flow achieves as much as a 28% leakage reduction with an average reduction of 12% after performing the proposed incremental placement and routing compared to the leading EDA synthesis and layout tool.