An Automated and Process-Portable Generator for Phase-Locked Loop

Zhongkai Wang, Minsoo Choi, Eric Y. Chang, J. Wright, Wooham Bae, S. Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt, Ayan Biswas, B. Nikolić, E. Alon
{"title":"An Automated and Process-Portable Generator for Phase-Locked Loop","authors":"Zhongkai Wang, Minsoo Choi, Eric Y. Chang, J. Wright, Wooham Bae, S. Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt, Ayan Biswas, B. Nikolić, E. Alon","doi":"10.1109/dac18074.2021.9586318","DOIUrl":null,"url":null,"abstract":"We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.","PeriodicalId":274161,"journal":{"name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 58th ACM/IEEE Design Automation Conference (DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/dac18074.2021.9586318","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.
锁相环的自动过程便携式发生器
我们提出了一个bang-bang锁相环(PLL)发生器,封装了其电路模块和完整锁相环系统的设计方法。生成器是完全自动化和参数化的,根据工艺特性和顶级规格生成布局和原理图。三个14GHz锁相环分别采用台积电16nm、格芯14nm和英特尔22nm技术进行了实例化,证明了该工艺的可移植性。不到四天的快速生成时间可以实现快速的锁相环设计和技术移植。采用台积电16nm工艺设计的锁相环在0.9V电源下的有效值抖动为565.4fs,功率为6.64mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信