Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya
{"title":"A Novel Packaging Platform for High-Performance Optical Engines in Hyperscale Data Center Applications","authors":"Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya","doi":"10.1109/ectc51906.2022.00074","DOIUrl":null,"url":null,"abstract":"Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ectc51906.2022.00074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.