SeReCon: A Trusted Environment for SoPC Design

Abstract

Problems of fraud, theft, impersonation and counterfeiting have migrated into computing and digital communication technology. Reconfigurable computing (RC) (e.g., FPGA) systems blur the boundary between hardware and software. As reconfigurable computing systems become more popular, concerns arise about their security and privacy. Run-time partial reconfiguration provides the flexibility of hardware, but at the same time may compromise security and integrity of the embedded system design. This paper discusses potential threats to such systems and describes SeReCon, a secure reconfiguration controller, as a countermeasure. SeReCon supports intellectual property protection within the FPGA and provides secure run-time management of designs within FPGA. The fundamentals of the SeReCon trusted computing base are described. Various IP Block processing scenarios are proposed. Early implementation results are reported.