A coefficient memory addressing scheme for VLSI implementation of FFT processors

Abstract

A novel scheme is presented for coefficient address generation in VLSI implementation of FFT processors. The scheme involves manipulation of address lines taking into consideration coefficient addresses required at various FFT stages. We show with the aid of examples that the scheme can lead to more efficient hardware realisations, with significant reduction in hardware for all FFT lengths. This leads to faster, more power and area efficient realisation of FFT processors than approaches published to date. The paper describes the scheme, its implementation in hardware, and presents results showing more than 80% reduction in area and power for almost all FFT lengths.