Reduced switching stress in high-voltage IGBT inverters via a three-level structure

Abstract

High voltage (3.3-4.5 kV) insulated gate bipolar transistors (HVIGBTs) are limited in SOA and ability to be effectively used in hard switched 2-level PWM inverters. The proposed operation sequence for the well known 3-level inverter allows use of HVIGBTs at near-rated voltage while cutting switching loss in half and allowing 3-level PWM for improved harmonics spectrum. Simulation and laboratory results prove the concept.