Optimization Combined Chip and Symbol Level Equalization for Downlink WCDMA Reception

Abstract

We consider iterative WCDMA receiver techniques for the UMTS FDD downlink. The popular LMMSE chip equalizer-correlator receiver does not exploit subspaces in partially loaded systems. This is in contrast to the symbol level LMMSE receiver, which is time-varying though, due to the scrambler, and hence too complex to implement. A compromise can be found by performing symbol level multi-stage Wiener filtering (MSWF), which is an iterative solution in which the complexity per iteration becomes comparable to twice that of the RAKE receiver. Since the MSWF works best when the input is white, better performance is obtained if the RAKE in each MSWF stage gets replaced by a chip equalizer-correlator. One of the main contributions here is to point out that the chip equalizer benefits from a separate optimization in every stage. This is shown through a mix of analysis and simulation results