{"title":"A Triple Deck Ceramic Sringle Chip Package For High Frequency Communication Integrated Circuits","authors":"M. Bedouani","doi":"10.1109/SBMO.1993.587230","DOIUrl":null,"url":null,"abstract":"High Frequency communication integrated circuits require specific packages with controlled impedance and very low attenuation. These IC’s use ECL like differential output gate structures. In this paper, we present full electrical design and experimental characterization of a high performance triple deck ceramic package based on shielded differential coplanar striplines used for (2-4 Gbitds) serial link circuits. Introduction Very high speed communication integrated circuits require specific packages with controlled impedance transmission lines and very low attenuation. High speed IC ‘s use differential gate structures: ECL Emitter Coupled Logic) and SCFL ( Source Coupled Eet Logic) respectively for silicon and GaAs technologies. We use a differential coplanar lines structure for high frequency packaging to avoid commutation noises and skew between the two output gate arms. On other hand, in order to have several isolated serial links in the: same edge of the chip, this structure is taken shielded. In cofired ceramic package techniques, conductors are made with tungsten paste (it’s resistivity is 14 times the copper resistivity). So, to reduce and control the conductor losses induced by the skin effects for high frequency applications, we use a shielded differential coplanar striplines [I] in 4.5 mm2 triple deck package (Figures 13). The minimum transmission line widht is 100 pm. Tapered lines are used to avoid impedance discontinuity ( the input and output pitches are respectively 300 pm and 1905 pm). The target characteristic impedances are SO Q and 100 Q respectively in single and differential modes. An analytical calculation method based on only simple transmission lines models is used for the electrical design of this structure. This analytical method is corraleted t o full 3D modelisation [ 21 and experimental characterization. Modelisation The scheme and the equivalent circuit model of the used shielded coplanar differential striplines are presented respectively in Figures 4 and 5. The L,Co,Cc and M parameters are determined by using a simple coupled lines models. The impedance of this structure is given by an analytical calculation : Zc=[ (L+M)/(CO+~C,)]~/~ and Zd=[ (L-M)/(C0+3Cc)] respectively in single and differential modes. L is the self inductance, CO is the plan capacitance, C, is the coupling capacitance and M is the mutual inductance. Comparison betweein analytical and 3D modelisation results are reported in Table 6. These results are very close within less than 5%. The influence of the ground transmission lines increases when the spacement between signal","PeriodicalId":219944,"journal":{"name":"SBMO International Microwave Conference/Brazil,","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"SBMO International Microwave Conference/Brazil,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMO.1993.587230","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
High Frequency communication integrated circuits require specific packages with controlled impedance and very low attenuation. These IC’s use ECL like differential output gate structures. In this paper, we present full electrical design and experimental characterization of a high performance triple deck ceramic package based on shielded differential coplanar striplines used for (2-4 Gbitds) serial link circuits. Introduction Very high speed communication integrated circuits require specific packages with controlled impedance transmission lines and very low attenuation. High speed IC ‘s use differential gate structures: ECL Emitter Coupled Logic) and SCFL ( Source Coupled Eet Logic) respectively for silicon and GaAs technologies. We use a differential coplanar lines structure for high frequency packaging to avoid commutation noises and skew between the two output gate arms. On other hand, in order to have several isolated serial links in the: same edge of the chip, this structure is taken shielded. In cofired ceramic package techniques, conductors are made with tungsten paste (it’s resistivity is 14 times the copper resistivity). So, to reduce and control the conductor losses induced by the skin effects for high frequency applications, we use a shielded differential coplanar striplines [I] in 4.5 mm2 triple deck package (Figures 13). The minimum transmission line widht is 100 pm. Tapered lines are used to avoid impedance discontinuity ( the input and output pitches are respectively 300 pm and 1905 pm). The target characteristic impedances are SO Q and 100 Q respectively in single and differential modes. An analytical calculation method based on only simple transmission lines models is used for the electrical design of this structure. This analytical method is corraleted t o full 3D modelisation [ 21 and experimental characterization. Modelisation The scheme and the equivalent circuit model of the used shielded coplanar differential striplines are presented respectively in Figures 4 and 5. The L,Co,Cc and M parameters are determined by using a simple coupled lines models. The impedance of this structure is given by an analytical calculation : Zc=[ (L+M)/(CO+~C,)]~/~ and Zd=[ (L-M)/(C0+3Cc)] respectively in single and differential modes. L is the self inductance, CO is the plan capacitance, C, is the coupling capacitance and M is the mutual inductance. Comparison betweein analytical and 3D modelisation results are reported in Table 6. These results are very close within less than 5%. The influence of the ground transmission lines increases when the spacement between signal