A Triple Deck Ceramic Sringle Chip Package For High Frequency Communication Integrated Circuits

M. Bedouani
{"title":"A Triple Deck Ceramic Sringle Chip Package For High Frequency Communication Integrated Circuits","authors":"M. Bedouani","doi":"10.1109/SBMO.1993.587230","DOIUrl":null,"url":null,"abstract":"High Frequency communication integrated circuits require specific packages with controlled impedance and very low attenuation. These IC’s use ECL like differential output gate structures. In this paper, we present full electrical design and experimental characterization of a high performance triple deck ceramic package based on shielded differential coplanar striplines used for (2-4 Gbitds) serial link circuits. Introduction Very high speed communication integrated circuits require specific packages with controlled impedance transmission lines and very low attenuation. High speed IC ‘s use differential gate structures: ECL Emitter Coupled Logic) and SCFL ( Source Coupled Eet Logic) respectively for silicon and GaAs technologies. We use a differential coplanar lines structure for high frequency packaging to avoid commutation noises and skew between the two output gate arms. On other hand, in order to have several isolated serial links in the: same edge of the chip, this structure is taken shielded. In cofired ceramic package techniques, conductors are made with tungsten paste (it’s resistivity is 14 times the copper resistivity). So, to reduce and control the conductor losses induced by the skin effects for high frequency applications, we use a shielded differential coplanar striplines [I] in 4.5 mm2 triple deck package (Figures 13). The minimum transmission line widht is 100 pm. Tapered lines are used to avoid impedance discontinuity ( the input and output pitches are respectively 300 pm and 1905 pm). The target characteristic impedances are SO Q and 100 Q respectively in single and differential modes. An analytical calculation method based on only simple transmission lines models is used for the electrical design of this structure. This analytical method is corraleted t o full 3D modelisation [ 21 and experimental characterization. Modelisation The scheme and the equivalent circuit model of the used shielded coplanar differential striplines are presented respectively in Figures 4 and 5. The L,Co,Cc and M parameters are determined by using a simple coupled lines models. The impedance of this structure is given by an analytical calculation : Zc=[ (L+M)/(CO+~C,)]~/~ and Zd=[ (L-M)/(C0+3Cc)] respectively in single and differential modes. L is the self inductance, CO is the plan capacitance, C, is the coupling capacitance and M is the mutual inductance. Comparison betweein analytical and 3D modelisation results are reported in Table 6. These results are very close within less than 5%. The influence of the ground transmission lines increases when the spacement between signal","PeriodicalId":219944,"journal":{"name":"SBMO International Microwave Conference/Brazil,","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"SBMO International Microwave Conference/Brazil,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMO.1993.587230","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

High Frequency communication integrated circuits require specific packages with controlled impedance and very low attenuation. These IC’s use ECL like differential output gate structures. In this paper, we present full electrical design and experimental characterization of a high performance triple deck ceramic package based on shielded differential coplanar striplines used for (2-4 Gbitds) serial link circuits. Introduction Very high speed communication integrated circuits require specific packages with controlled impedance transmission lines and very low attenuation. High speed IC ‘s use differential gate structures: ECL Emitter Coupled Logic) and SCFL ( Source Coupled Eet Logic) respectively for silicon and GaAs technologies. We use a differential coplanar lines structure for high frequency packaging to avoid commutation noises and skew between the two output gate arms. On other hand, in order to have several isolated serial links in the: same edge of the chip, this structure is taken shielded. In cofired ceramic package techniques, conductors are made with tungsten paste (it’s resistivity is 14 times the copper resistivity). So, to reduce and control the conductor losses induced by the skin effects for high frequency applications, we use a shielded differential coplanar striplines [I] in 4.5 mm2 triple deck package (Figures 13). The minimum transmission line widht is 100 pm. Tapered lines are used to avoid impedance discontinuity ( the input and output pitches are respectively 300 pm and 1905 pm). The target characteristic impedances are SO Q and 100 Q respectively in single and differential modes. An analytical calculation method based on only simple transmission lines models is used for the electrical design of this structure. This analytical method is corraleted t o full 3D modelisation [ 21 and experimental characterization. Modelisation The scheme and the equivalent circuit model of the used shielded coplanar differential striplines are presented respectively in Figures 4 and 5. The L,Co,Cc and M parameters are determined by using a simple coupled lines models. The impedance of this structure is given by an analytical calculation : Zc=[ (L+M)/(CO+~C,)]~/~ and Zd=[ (L-M)/(C0+3Cc)] respectively in single and differential modes. L is the self inductance, CO is the plan capacitance, C, is the coupling capacitance and M is the mutual inductance. Comparison betweein analytical and 3D modelisation results are reported in Table 6. These results are very close within less than 5%. The influence of the ground transmission lines increases when the spacement between signal
用于高频通信集成电路的三层陶瓷单芯片封装
高频通信集成电路需要具有可控阻抗和极低衰减的特定封装。这些集成电路使用像ECL的差分输出门结构。在本文中,我们提出了一种基于屏蔽差分共面带状线的高性能三层陶瓷封装的完整电气设计和实验特性,该封装用于(2-4 Gbitds)串行链路电路。非常高速的通信集成电路需要具有可控阻抗传输线和非常低衰减的特定封装。高速集成电路使用差分门结构:ECL(发射极耦合逻辑)和SCFL(源耦合Eet逻辑)分别用于硅和GaAs技术。我们使用差分共面线结构进行高频封装,以避免换流噪声和两个输出门臂之间的倾斜。另一方面,为了在芯片的同一边缘有几个隔离的串行链路,这种结构被采取屏蔽。在共烧陶瓷封装技术中,导体由钨膏制成(其电阻率是铜电阻率的14倍)。因此,为了减少和控制高频应用中由趋肤效应引起的导体损耗,我们在4.5 mm2三层封装中使用屏蔽差分共面带状线[I](图13)。传输线宽度最小为100pm。使用锥形线以避免阻抗不连续(输入和输出螺距分别为300 pm和1905 pm)。在单模式和差分模式下,目标特性阻抗分别为10q和100q。该结构的电气设计采用了基于简单传输线模型的解析计算方法。这种分析方法与全3D建模[21]和实验表征相关。所使用的屏蔽共面差分带状线的方案和等效电路模型分别如图4和图5所示。L,Co,Cc和M参数通过使用简单的耦合线模型来确定。该结构的阻抗由解析计算得到:单模和差模下Zc=[(L+M)/(CO+~C,)]~/~和Zd=[(L-M)/(C0+3Cc)]。L为自感,CO为规划电容,C为耦合电容,M为互感。分析和三维建模结果的比较见表6。这些结果非常接近,误差小于5%。地面传输线的影响随着信号间距的增大而增大
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