A High-performance Charge Pump for 40 nm Delay Locked Loops

Abstract

A highly current matched charge pump (CP) is proposed to improve the precision of the output clock for a delay-locked loop (DLL). The presented CP based on source-switched structure achieves good matching of charging and discharging currents over a broad dynamic range by introducing a novel rail-to-rail operational amplifier. The stable output voltage of the modified charge pump dramatically reduces the jitter of all output clocks in the locking state. Simulation results at a 1.2V supply voltage and a 40 nm COMS technology demonstrate the maximum mismatching ratio of charging and discharging currents decreases from 26.3% to 5.4% over the operating range of 0.2~1V. Furthermore, compared with the conventional charge pump, the maximum reduction magnitude of jitter for the related output clock is as much as 74.3% at the reference input clock of 1GHz.