Modelling the dynamic response of on-chip decoupling capacitors

Abstract

High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models.