Optimization and Comparison of Various Subnanosecond Bipolar IC's with Low Power Dissipation

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468769

R. Ranfft, H. Rein

引用次数: 4

Abstract

A simple rapidly converging optimization routine for non saturated digital IC's is described. It yields the minimum delay for a given power dissipation per gate by varying easily controllable technological parameters. The basic gates of various circuit techniques are compared using this routine.

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各种低功耗亚纳秒双极集成电路的优化与比较

介绍了一种简单的非饱和数字集成电路快速收敛优化程序。它通过改变易于控制的技术参数，在给定的每门功耗下产生最小的延迟。使用此程序对各种电路技术的基本门进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC 80: 6th European Solid State Circuits Conference

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