Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators

Abstract

This paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip.