A high-speed AES architecture implementation

Abstract

We present in this paper a high performance implementation for the Advanced Encryption Standard (AES) standard. The design goal is directed toward efficient implementation of an AES cryptocore. The proposed architecture exhibits parallelism by concurrently processing all the bytes of a data block and computes each round key on-the-fly. The design implements both AES encryption and decryption by efficiently sharing the complex design modules. The proposed high-speed iterative implementation performing the AES operations in 11 clock cycles was synthesized for ALTERA's Cyclone II FPGA.