MTJ-based "normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme

Abstract

MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for high speed operation and considered not suited for lower level cache memory. In this work, we have developed L2 and L3 cache memory based on thermal stability factor engineered pMTJ with 2T-2MTJ and 1T-1MTJ memory cell and novel error handling scheme. These techniques reduce 75% energy with 2% performance overhead compared to SRAM-based l2 and L3 cache memory.