SO(DA)2: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk)

Antonino Tumeo, Nicolas Bohm Agostini, S. Curzel, Ankur Limaye, Cheng Tan, Vinay C. Amatya, Marco Minutoli, Vito Giovanni Castellana, Ang Li, J. Manzano
{"title":"SO(DA)2: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk)","authors":"Antonino Tumeo, Nicolas Bohm Agostini, S. Curzel, Ankur Limaye, Cheng Tan, Vinay C. Amatya, Marco Minutoli, Vito Giovanni Castellana, Ang Li, J. Manzano","doi":"10.4230/OASIcs.PARMA-DITAM.2022.1","DOIUrl":null,"url":null,"abstract":"Modern data analysis applications are complex workflows composed of algorithms with diverse behaviors. They may include digital signal processing, data filtering, reduction, compression, graph algorithms, and machine learning. Their performance is highly dependent on the volume, the velocity, and the structure of the data. They are used in many different domains (from small, embedded devices, to large-scale, high-performance computing systems) but in all cases they need to provide answers with very low latency to enable real-time decision making and autonomy. Coarse-grained reconfigurable arrays (CGRAs), i.e., architectures composed of functional units able to perform complex operations interconnected through a network-on-chip and configure the datapath to map complex kernels, are a promising platform to accelerate these applications thanks to their adaptability. They provide higher flexibility than application-specific integrated circuits (ASICs) while offering increased energy efficiency and faster reconfiguration speed with respect to field-programmable gate arrays (FPGAs). However, designing and specializing CGRAs requires significant efforts. The inherent flexibility of these devices makes the application mapping process equally important to the hardware design generation. To obtain efficient systems, approaches that simultaneously considers software and hardware optimizations are necessary. In this paper, we discuss the Software Defined Architectures for Data Analytics (SO(DA) 2 ) toolchain, an end-to-end hardware/software codesign framework to generate custom reconfigurable architectures for data analytics applications. (SO(DA) 2 ) is composed of a high-level compiler (SODA-OPT) and a hardware generator (OpenCGRA) and can automatically explore and generate optimal CGRA designs starting from high-level programming frameworks. SO(DA) 2 considers partial dynamic reconfiguration as key element of the system design. We discuss the various elements of the framework and demonstrate the flow on the case study of a partial dynamic reconfigurable CGRA design for data streaming applications. Acknowledgements The research described in this paper is part of the Data-Model Convergence (DMC) Initiative at Pacific Northwest National Laboratory. It was conducted under the Laboratory Directed Research and Development Program at PNNL, a multiprogram national laboratory operated by Battelle for the U.S. Department of Energy.","PeriodicalId":436349,"journal":{"name":"PARMA-DITAM@HiPEAC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"PARMA-DITAM@HiPEAC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.1","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Modern data analysis applications are complex workflows composed of algorithms with diverse behaviors. They may include digital signal processing, data filtering, reduction, compression, graph algorithms, and machine learning. Their performance is highly dependent on the volume, the velocity, and the structure of the data. They are used in many different domains (from small, embedded devices, to large-scale, high-performance computing systems) but in all cases they need to provide answers with very low latency to enable real-time decision making and autonomy. Coarse-grained reconfigurable arrays (CGRAs), i.e., architectures composed of functional units able to perform complex operations interconnected through a network-on-chip and configure the datapath to map complex kernels, are a promising platform to accelerate these applications thanks to their adaptability. They provide higher flexibility than application-specific integrated circuits (ASICs) while offering increased energy efficiency and faster reconfiguration speed with respect to field-programmable gate arrays (FPGAs). However, designing and specializing CGRAs requires significant efforts. The inherent flexibility of these devices makes the application mapping process equally important to the hardware design generation. To obtain efficient systems, approaches that simultaneously considers software and hardware optimizations are necessary. In this paper, we discuss the Software Defined Architectures for Data Analytics (SO(DA) 2 ) toolchain, an end-to-end hardware/software codesign framework to generate custom reconfigurable architectures for data analytics applications. (SO(DA) 2 ) is composed of a high-level compiler (SODA-OPT) and a hardware generator (OpenCGRA) and can automatically explore and generate optimal CGRA designs starting from high-level programming frameworks. SO(DA) 2 considers partial dynamic reconfiguration as key element of the system design. We discuss the various elements of the framework and demonstrate the flow on the case study of a partial dynamic reconfigurable CGRA design for data streaming applications. Acknowledgements The research described in this paper is part of the Data-Model Convergence (DMC) Initiative at Pacific Northwest National Laboratory. It was conducted under the Laboratory Directed Research and Development Program at PNNL, a multiprogram national laboratory operated by Battelle for the U.S. Department of Energy.
SO(DA)2:专用可重构架构的端到端生成(特邀演讲)
现代数据分析应用程序是由具有不同行为的算法组成的复杂工作流。它们可能包括数字信号处理、数据滤波、约简、压缩、图算法和机器学习。它们的性能高度依赖于数据的体积、速度和结构。它们用于许多不同的领域(从小型嵌入式设备到大型高性能计算系统),但在所有情况下,它们都需要以非常低的延迟提供答案,以实现实时决策和自治。粗粒度可重构阵列(CGRAs),即由功能单元组成的架构,能够执行通过片上网络相互连接的复杂操作,并配置数据路径以映射复杂的内核,由于其适应性,是加速这些应用程序的有前途的平台。与专用集成电路(asic)相比,它们具有更高的灵活性,同时与现场可编程门阵列(fpga)相比,它们具有更高的能效和更快的重新配置速度。然而,设计和专业化CGRAs需要付出巨大的努力。这些设备固有的灵活性使得应用程序映射过程对硬件设计生成同样重要。为了获得高效的系统,同时考虑软件和硬件优化的方法是必要的。在本文中,我们讨论了用于数据分析的软件定义架构(SO(DA) 2)工具链,这是一个端到端的硬件/软件协同设计框架,用于为数据分析应用程序生成自定义的可重构架构。(SO(DA) 2)由高级编译器(SODA-OPT)和硬件生成器(OpenCGRA)组成,可以从高级编程框架开始自动探索和生成最优的CGRA设计。SO(DA) 2将局部动态重构作为系统设计的关键要素。我们讨论了框架的各种元素,并在数据流应用程序的部分动态可重构CGRA设计的案例研究中演示了流程。本文中描述的研究是太平洋西北国家实验室数据模型融合(DMC)计划的一部分。它是在PNNL的实验室指导研究和开发计划下进行的,PNNL是一个由Battelle为美国能源部运营的多项目国家实验室。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信