Rupinder Kaur, Jaya Madan, Rajnish Sharma, R. Pandey, R. Chaujar
{"title":"Capacitive Analysis of Hetero Material Gate PNIN-DG-TFET Over Diverge Temperature Range for Superior RF/Microwave Performance","authors":"Rupinder Kaur, Jaya Madan, Rajnish Sharma, R. Pandey, R. Chaujar","doi":"10.1109/EDKCON.2018.8770491","DOIUrl":null,"url":null,"abstract":"Tunnel FETs overcome the limitations of conventional MOSFETs and offer wide scope for high speed switching analog/RF applications. In most of the research papers, the main focus is to improve the ION current and decrease the ambipolar current in TFETs. However, the parasitic capacitances and ambient temperature also play a crucial role in the performance analysis of the device. Here, in this research work, a Hetero-Material gate, n+ source pocket, dual-gate, TFET (HMG-PNIN-DG-TFET)is proposed for superior switching ratio and its CV analysis is presented for distinct temperature range. The parasitic capacitances have been analyzed with respect to gate and drain biasing for temperature range from 200K to 400K. In addition to it, the influence of temperature variations on transconductance (gm), cut-off frequency (fT)and intrinsic delay (τ)has also been evaluated. Analysis gives a huge prospect to realize efficient analog and RF circuitry with the device proposed (i.e. HMG-PNIN-DG-TFET)in this paper.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770491","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Tunnel FETs overcome the limitations of conventional MOSFETs and offer wide scope for high speed switching analog/RF applications. In most of the research papers, the main focus is to improve the ION current and decrease the ambipolar current in TFETs. However, the parasitic capacitances and ambient temperature also play a crucial role in the performance analysis of the device. Here, in this research work, a Hetero-Material gate, n+ source pocket, dual-gate, TFET (HMG-PNIN-DG-TFET)is proposed for superior switching ratio and its CV analysis is presented for distinct temperature range. The parasitic capacitances have been analyzed with respect to gate and drain biasing for temperature range from 200K to 400K. In addition to it, the influence of temperature variations on transconductance (gm), cut-off frequency (fT)and intrinsic delay (τ)has also been evaluated. Analysis gives a huge prospect to realize efficient analog and RF circuitry with the device proposed (i.e. HMG-PNIN-DG-TFET)in this paper.