Seung Jun Lee, J. Ha, Jeawook Shin, Hyunchol Shin, Y. Eo
{"title":"A CMOS mobile TV tuner with precise RF gain control and fast locking PLL for multiband FM/T-DMB/DAB applications","authors":"Seung Jun Lee, J. Ha, Jeawook Shin, Hyunchol Shin, Y. Eo","doi":"10.1109/RWS.2011.5725424","DOIUrl":null,"url":null,"abstract":"A fully integrated tuner IC based on low-IF architecture is developed for triple-band FM/T-DMB/DAB applications. A precise RF gain control with 50 dB dynamic range is achieved in RF VGA by employing a capacitive ladder type attenuator. A novel coarse tuning scheme based on a RF frequency-to-digital converter allows fast and agile automatic VCO frequency calibration, leading to fast locking in PLL. Implemented in 0.13 µm CMOS, the tuner consumes 57 mA from 1.2 V supply. Measured results are NF < 1.5 dB at the maximum gain and IIP3 > 0 dBm with LNA bypassed. The integrated phase noise of ΔΣ fractional-N PLL is less than 1 rms degree, and the coarse tuning time is less than 2.03 µsec.","PeriodicalId":250672,"journal":{"name":"2011 IEEE Radio and Wireless Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2011.5725424","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A fully integrated tuner IC based on low-IF architecture is developed for triple-band FM/T-DMB/DAB applications. A precise RF gain control with 50 dB dynamic range is achieved in RF VGA by employing a capacitive ladder type attenuator. A novel coarse tuning scheme based on a RF frequency-to-digital converter allows fast and agile automatic VCO frequency calibration, leading to fast locking in PLL. Implemented in 0.13 µm CMOS, the tuner consumes 57 mA from 1.2 V supply. Measured results are NF < 1.5 dB at the maximum gain and IIP3 > 0 dBm with LNA bypassed. The integrated phase noise of ΔΣ fractional-N PLL is less than 1 rms degree, and the coarse tuning time is less than 2.03 µsec.