Increased thin film wiring density by stacked vias

Abstract

Via stacking has been used successfully over the years during the fabrication of semiconductor personalization layers. This structure requires Chem-mech planarization to fabricate via studs and discrete wiring. In contrast, non planar structures result when sequential layers of metal and dielectric are deposited without the planarization step. During the fabrication of MCM-D, polyimide dielectric films are patterned to create a via opening, allowing for level-to-level connection. Traditionally, these vias are not stacked. In multilevel thin films, the more common via structures are either staircase or spiral. Even when the vias are co-centered, as is the case for power vias of some MCM-D products, the via diameter is increased from one level to the next level producing a reverse pyramid structure. IBM has developed stacked vias technology which simplifies and adds flexibility to the thin film design. This paper will discuss the processing aspects of stacked vias on a non-planar structure, and will present a mechanical finite element model for various via diameters (5, 10, 15, 20, and 25 um) on a four metal level structure. It will also contrast the effect on topography and planarity of stacked and non-stacked via structures.