{"title":"A New Discrete-Time Model of Fractional-Order PLL","authors":"R. El-Khazali, S. Momani, I. Batiha","doi":"10.1109/icspis51252.2020.9340137","DOIUrl":null,"url":null,"abstract":"this work presents a new discrete-time fractional-order phase-locked loop (DTFoPLL). The new model is developed by introducing a 1st-order z-transfer function that approximates a dynamic fractional-order discrete-time integrator that depends on its fractional order. Such structure is used to realize both the discrete-time fractional-order filter (DTFoF) and a fractional-order digital controlled-oscillator (FoDCO) of the PLL. The flexibility of the design follows from choosing low-order PLLs (between $\\boldsymbol{0.1\\leq\\alpha\\leq 0.2)}$ that provides wider bandwidth and requires lower gains than its integer-order counter parts. The main points of this work are illustrated via numerical simulation.","PeriodicalId":373750,"journal":{"name":"2020 3rd International Conference on Signal Processing and Information Security (ICSPIS)","volume":"482 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 3rd International Conference on Signal Processing and Information Security (ICSPIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icspis51252.2020.9340137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
this work presents a new discrete-time fractional-order phase-locked loop (DTFoPLL). The new model is developed by introducing a 1st-order z-transfer function that approximates a dynamic fractional-order discrete-time integrator that depends on its fractional order. Such structure is used to realize both the discrete-time fractional-order filter (DTFoF) and a fractional-order digital controlled-oscillator (FoDCO) of the PLL. The flexibility of the design follows from choosing low-order PLLs (between $\boldsymbol{0.1\leq\alpha\leq 0.2)}$ that provides wider bandwidth and requires lower gains than its integer-order counter parts. The main points of this work are illustrated via numerical simulation.