A 0.65V, 1.9mW CMOS low-noise amplifier at 5GHz

Abstract

An ultra low-voltage (0.65 V), 5 GHz low noise amplifier (LNA) has been designed, laid out and simulated using Spectre simulator in a standard TSMC 0.18/spl mu/m CMOS technology. The proposed LNA achieves better performance than conventional cascode topology and are confirmed by simulation results. The LNA provides a high gain of 20 dB, a noise figure of 1.4 dB, power dissipation of 1.9 mW from a 0.65 V power supply. To the best of author's knowledge this is the lowest voltage supply CMOS LNA design reported to date.