Generic Expressions for Early Estimation of Performance of Binary Multipliers

Abstract

The paper proposes generic expressions for early design phase and accurate estimation of the performance of binary multipliers of $n$-bits in length using eight kinds of traditional adders. The performance of n-bits multipliers using different adders can be quickly assessed in theory by using proposed generic expressions without actual circuits. Performance parameters that are considered are namely the number of stages, gate counts, required area, energy dissipated and worst-case gate level delay. Full adder array is applied to design RCA (Ripple Carry Adder) based multiplier; the number of adder cells at different stages are found. Then, multi-length adder array is designed for multiplier using multi-bits adders; the number of adders with different lengths are analyzed at different stages. Meanwhile, proposed expressions are validated against actual designs; estimated results using proposed expressions show in good agreement with results of actual circuits. Finally, different multipliers are compared in terms of their performances by using proposed expressions. Multipliers using KSA (Kogge-Stone adder) and CSLA (Carry Select adder) require the highest area ($3370 \mu m^{2}$ for $n=16$) and consume the highest energy dissipation (2.5E-13J). The RCA based multiplier requires the lowest number of gates, area ($1637.96 \mu m^{2}$) and energy dissipation (1.2791E-13J). Also, the worst-case delay for KSA based multiplier and SA (Sklansky adder) based multiplier is lowest (only 60 gate level delays), while that for RCA based multiplier is highest (209 gate level delays).